// NGREG 34
return strdup (
"=PC	pc\n"
"=BP	x29\n"
"=SP	sp\n"
"=SN	x8\n"
"=A0	x0\n"
"=A1	x1\n"
"=A2	x2\n"
"=A3	x3\n"
"=ZF	zf\n"
"=SF	nf\n"
"=OF	vf\n"
"=CF	cf\n"
#if 0
"=SN	ox8\n"
#endif
"gpr	x0	.64	0	0\n"
"gpr	x1	.64	8	0\n"
"gpr	x2	.64	16	0\n"
"gpr	x3	.64	24	0\n"
"gpr	x4	.64	32	0\n"
"gpr	x5	.64	40	0\n"
"gpr	x6	.64	48	0\n"
"gpr	x7	.64	56	0\n"
"gpr	x8	.64	64	0\n"
"gpr	x9	.64	72	0\n"
"gpr	x10	.64	80	0\n"
"gpr	x11	.64	88	0\n"
"gpr	x12	.64	96	0\n"
"gpr	x13	.64	104	0\n"
"gpr	x14	.64	112	0\n"
"gpr	x15	.64	120	0\n"
"gpr	x16	.64	128	0\n"
"gpr	x17	.64	136	0\n"
"gpr	x18	.64	144	0\n"
"gpr	x19	.64	152	0\n"
"gpr	x20	.64	160	0\n"
"gpr	x21	.64	168	0\n"
"gpr	x22	.64	176	0\n"
"gpr	x23	.64	184	0\n"
"gpr	x24	.64	192	0\n"
"gpr	x25	.64	200	0\n"
"gpr	x26	.64	208	0\n"
"gpr	x27	.64	216	0\n"
"gpr	x28	.64	224	0\n"
"gpr	x29	.64	232	0\n"
"gpr	x30	.64	240	0\n"
"gpr	sp	.64	248	0\n"
"gpr	pc	.64	256	0\n"

// 8 bit

"gpr	b0	.8	0	0\n"
"gpr	b1	.8	8	0\n"
"gpr	b2	.8	16	0\n"
"gpr	b3	.8	24	0\n"
"gpr	b4	.8	32	0\n"
"gpr	b5	.8	40	0\n"
"gpr	b6	.8	48	0\n"
"gpr	b7	.8	56	0\n"
"gpr	b8	.8	64	0\n"
"gpr	b9	.8	72	0\n"
"gpr	b10	.8	80	0\n"
"gpr	b11	.8	88	0\n"
"gpr	b12	.8	96	0\n"
"gpr	b13	.8	104	0\n"
"gpr	b14	.8	112	0\n"
"gpr	b15	.8	120	0\n"
"gpr	b16	.8	128	0\n"
"gpr	b17	.8	136	0\n"
"gpr	b18	.8	144	0\n"
"gpr	b19	.8	152	0\n"
"gpr	b20	.8	160	0\n"
"gpr	b21	.8	168	0\n"
"gpr	b22	.8	176	0\n"
"gpr	b23	.8	184	0\n"
"gpr	b24	.8	192	0\n"
"gpr	b25	.8	200	0\n"
"gpr	b26	.8	208	0\n"
"gpr	b27	.8	216	0\n"
"gpr	b28	.8	224	0\n"
"gpr	b29	.8	232	0\n"
"gpr	b30	.8	240	0\n"
"gpr	bsp	.8	248	0\n"

// 16 bit

"gpr	h0	.16	0	0\n"
"gpr	h1	.16	8	0\n"
"gpr	h2	.16	16	0\n"
"gpr	h3	.16	24	0\n"
"gpr	h4	.16	32	0\n"
"gpr	h5	.16	40	0\n"
"gpr	h6	.16	48	0\n"
"gpr	h7	.16	56	0\n"
"gpr	h8	.16	64	0\n"
"gpr	h9	.16	72	0\n"
"gpr	h10	.16	80	0\n"
"gpr	h11	.16	88	0\n"
"gpr	h12	.16	96	0\n"
"gpr	h13	.16	104	0\n"
"gpr	h14	.16	112	0\n"
"gpr	h15	.16	120	0\n"
"gpr	h16	.16	128	0\n"
"gpr	h17	.16	136	0\n"
"gpr	h18	.16	144	0\n"
"gpr	h19	.16	152	0\n"
"gpr	h20	.16	160	0\n"
"gpr	h21	.16	168	0\n"
"gpr	h22	.16	176	0\n"
"gpr	h23	.16	184	0\n"
"gpr	h24	.16	192	0\n"
"gpr	h25	.16	200	0\n"
"gpr	h26	.16	208	0\n"
"gpr	h27	.16	216	0\n"
"gpr	h28	.16	224	0\n"
"gpr	h29	.16	232	0\n"
"gpr	h30	.16	240	0\n"

// 32 bit

"gpr	w0	.32	0	0\n"
"gpr	w1	.32	8	0\n"
"gpr	w2	.32	16	0\n"
"gpr	w3	.32	24	0\n"
"gpr	w4	.32	32	0\n"
"gpr	w5	.32	40	0\n"
"gpr	w6	.32	48	0\n"
"gpr	w7	.32	56	0\n"
"gpr	w8	.32	64	0\n"
"gpr	w9	.32	72	0\n"
"gpr	w10	.32	80	0\n"
"gpr	w11	.32	88	0\n"
"gpr	w12	.32	96	0\n"
"gpr	w13	.32	104	0\n"
"gpr	w14	.32	112	0\n"
"gpr	w15	.32	120	0\n"
"gpr	w16	.32	128	0\n"
"gpr	w17	.32	136	0\n"
"gpr	w18	.32	144	0\n"
"gpr	w19	.32	152	0\n"
"gpr	w20	.32	160	0\n"
"gpr	w21	.32	168	0\n"
"gpr	w22	.32	176	0\n"
"gpr	w23	.32	184	0\n"
"gpr	w24	.32	192	0\n"
"gpr	w25	.32	200	0\n"
"gpr	w26	.32	208	0\n"
"gpr	w27	.32	216	0\n"
"gpr	w28	.32	224	0\n"
"gpr	w29	.32	232	0\n"
"gpr	w30	.32	240	0\n"
"gpr	wsp	.32	248	0\n"
"gpr	wzr	.32	?	0\n"

// FPU registers
// 32-bit single precision
"fpu	s0	.32	0	0\n"
"fpu	s1	.32	16	0\n"
"fpu	s2	.32	32	0\n"
"fpu	s3	.32	48	0\n"
"fpu	s4	.32	64	0\n"
"fpu	s5	.32	80	0\n"
"fpu	s6	.32	96	0\n"
"fpu	s7	.32	112	0\n"
"fpu	s8	.32	128	0\n"
"fpu	s9	.32	144	0\n"
"fpu	s10	.32	160	0\n"
"fpu	s11	.32	176	0\n"
"fpu	s12	.32	192	0\n"
"fpu	s13	.32	208	0\n"
"fpu	s14	.32	224	0\n"
"fpu	s15	.32	240	0\n"
"fpu	s16	.32	256	0\n"
"fpu	s17	.32	272	0\n"
"fpu	s18	.32	288	0\n"
"fpu	s19	.32	304	0\n"
"fpu	s20	.32	320	0\n"
"fpu	s21	.32	336	0\n"
"fpu	s22	.32	352	0\n"
"fpu	s23	.32	368	0\n"
"fpu	s24	.32	384	0\n"
"fpu	s25	.32	400	0\n"
"fpu	s26	.32	416	0\n"
"fpu	s27	.32	432	0\n"
"fpu	s28	.32	448	0\n"
"fpu	s29	.32	464	0\n"
"fpu	s30	.32	480	0\n"
"fpu	s31	.32	496	0\n"

// 64-bit double precision
"fpu	d0	.64	0	0\n"
"fpu	d1	.64	16	0\n"
"fpu	d2	.64	32	0\n"
"fpu	d3	.64	48	0\n"
"fpu	d4	.64	64	0\n"
"fpu	d5	.64	80	0\n"
"fpu	d6	.64	96	0\n"
"fpu	d7	.64	112	0\n"
"fpu	d8	.64	128	0\n"
"fpu	d9	.64	144	0\n"
"fpu	d10	.64	160	0\n"
"fpu	d11	.64	176	0\n"
"fpu	d12	.64	192	0\n"
"fpu	d13	.64	208	0\n"
"fpu	d14	.64	224	0\n"
"fpu	d15	.64	240	0\n"
"fpu	d16	.64	256	0\n"
"fpu	d17	.64	272	0\n"
"fpu	d18	.64	288	0\n"
"fpu	d19	.64	304	0\n"
"fpu	d20	.64	320	0\n"
"fpu	d21	.64	336	0\n"
"fpu	d22	.64	352	0\n"
"fpu	d23	.64	368	0\n"
"fpu	d24	.64	384	0\n"
"fpu	d25	.64	400	0\n"
"fpu	d26	.64	416	0\n"
"fpu	d27	.64	432	0\n"
"fpu	d28	.64	448	0\n"
"fpu	d29	.64	464	0\n"
"fpu	d30	.64	480	0\n"
"fpu	d31	.64	496	0\n"

// 128-bit vector registers
"fpu	v0	.128	0	0\n"
"fpu	v1	.128	16	0\n"
"fpu	v2	.128	32	0\n"
"fpu	v3	.128	48	0\n"
"fpu	v4	.128	64	0\n"
"fpu	v5	.128	80	0\n"
"fpu	v6	.128	96	0\n"
"fpu	v7	.128	112	0\n"
"fpu	v8	.128	128	0\n"
"fpu	v9	.128	144	0\n"
"fpu	v10	.128	160	0\n"
"fpu	v11	.128	176	0\n"
"fpu	v12	.128	192	0\n"
"fpu	v13	.128	208	0\n"
"fpu	v14	.128	224	0\n"
"fpu	v15	.128	240	0\n"
"fpu	v16	.128	256	0\n"
"fpu	v17	.128	272	0\n"
"fpu	v18	.128	288	0\n"
"fpu	v19	.128	304	0\n"
"fpu	v20	.128	320	0\n"
"fpu	v21	.128	336	0\n"
"fpu	v22	.128	352	0\n"
"fpu	v23	.128	368	0\n"
"fpu	v24	.128	384	0\n"
"fpu	v25	.128	400	0\n"
"fpu	v26	.128	416	0\n"
"fpu	v27	.128	432	0\n"
"fpu	v28	.128	448	0\n"
"fpu	v29	.128	464	0\n"
"fpu	v30	.128	480	0\n"
"fpu	v31	.128	496	0\n"

"gpr	pstate	.64	264	0\n"
"flg	fstate	.64	264	0   _____tfiae_____________j__qvczn\n"
"flg	vf	.1	264.28	0	overflow\n"
"flg	cf	.1	264.29	0	carry\n"
"flg	zf	.1	264.30	0	zero\n"
"flg	nf	.1	264.31	0	sign\n"
// extra linux regs in struct
//"gpr	ox0	.64	272	0\n"
//"gpr	sysno	.64	280	0\n"

// probably wrong
#if 0
"gpr	nf	.1	.256	0	sign\n" // msb bit of last op
"gpr	zf	.1	.257	0	zero\n" // set if last op is 0
"gpr	cf	.1	.258	0	carry\n" // set if last op carries
"gpr	vf	.1	.259	0	overflow\n" // set if overflows
#endif
);