// radare - MIT - Copyright 2026 - pancake - register block of x86_64_debug_cpu_state after the leading fpu/sse state
return strdup (
"=PC	rip\n"
"=SP	rsp\n"
"=BP	rbp\n"
"=SN	rax\n"
"=A0	rdi\n"
"=A1	rsi\n"
"=A2	rdx\n"
"=A3	rcx\n"
"=A4	r8\n"
"=A5	r9\n"
"seg	gs	.64	0	0\n"
"seg	fs	.64	8	0\n"
"seg	es	.64	16	0\n"
"seg	ds	.64	24	0\n"
"gpr	r15	.64	32	0\n"
"gpr	r15d	.32	32	0\n"
"gpr	r14	.64	40	0\n"
"gpr	r14d	.32	40	0\n"
"gpr	r13	.64	48	0\n"
"gpr	r13d	.32	48	0\n"
"gpr	r12	.64	56	0\n"
"gpr	r12d	.32	56	0\n"
"gpr	r11	.64	64	0\n"
"gpr	r11d	.32	64	0\n"
"gpr	r10	.64	72	0\n"
"gpr	r10d	.32	72	0\n"
"gpr	r9	.64	80	0\n"
"gpr	r9d	.32	80	0\n"
"gpr	r8	.64	88	0\n"
"gpr	r8d	.32	88	0\n"
"gpr	rbp	.64	96	0\n"
"gpr	ebp	.32	96	0\n"
"gpr	rsi	.64	104	0\n"
"gpr	esi	.32	104	0\n"
"gpr	si	.16	104	0\n"
"gpr	sil	.8	104	0\n"
"gpr	rdi	.64	112	0\n"
"gpr	edi	.32	112	0\n"
"gpr	di	.16	112	0\n"
"gpr	dil	.8	112	0\n"
"gpr	rdx	.64	120	0\n"
"gpr	edx	.32	120	0\n"
"gpr	dx	.16	120	0\n"
"gpr	dl	.8	120	0\n"
"gpr	rcx	.64	128	0\n"
"gpr	ecx	.32	128	0\n"
"gpr	cx	.16	128	0\n"
"gpr	cl	.8	128	0\n"
"gpr	rbx	.64	136	0\n"
"gpr	ebx	.32	136	0\n"
"gpr	bx	.16	136	0\n"
"gpr	bl	.8	136	0\n"
"gpr	rax	.64	144	0\n"
"gpr	eax	.32	144	0\n"
"gpr	ax	.16	144	0\n"
"gpr	al	.8	144	0\n"
"gpr	vector	.64	152	0\n"
"gpr	errcode	.64	160	0\n"
"gpr	rip	.64	168	0\n"
"seg	cs	.64	176	0\n"
"gpr	rflags	.64	184	0	c1p.a.zstido.n.rv\n"
"gpr	eflags	.32	184	0	c1p.a.zstido.n.rv\n"
"flg	cf	.1	.1472	0	carry\n"
"flg	pf	.1	.1474	0	parity\n"
"flg	af	.1	.1476	0	adjust\n"
"flg	zf	.1	.1478	0	zero\n"
"flg	sf	.1	.1479	0	sign\n"
"flg	tf	.1	.1480	0	trap\n"
"flg	if	.1	.1481	0	interrupt\n"
"flg	df	.1	.1482	0	direction\n"
"flg	of	.1	.1483	0	overflow\n"
"gpr	rsp	.64	192	0\n"
"gpr	esp	.32	192	0\n"
"gpr	sp	.16	192	0\n"
"gpr	spl	.8	192	0\n"
"seg	ss	.64	200	0\n"
);