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			(property "Manufacturer1 Example" "YAGEO PHYCOMP"
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			(property "Author" "CERN DEM JLC"
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		(symbol "pxie-wren-altium-import:VTT_DDR4-PS"
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			(in_bom yes)
			(on_board yes)
			(property "Reference" "#PWR"
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			(property "Value" "VTT_DDR4-PS"
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		(members "DDR4-PS.DQ[31..0]" "DDR4-PS.DM[3..0]" "DDR4-PS.DQS_P[3..0]" "DDR4-PS.DQS_N[3..0]"
			"DDR4-PS.A[13..0]" "DDR4-PS.CK_P" "DDR4-PS.CK_N" "DDR4-PS.CKE" "DDR4-PS.RSTN"
			"DDR4-PS.ACTN" "DDR4-PS.PAR" "DDR4-PS.CSN" "DDR4-PS.ODT" "DDR4-PS.BA[1..0]"
			"DDR4-PS.BG0" "DDR4-PS.ALERTN" "DDR4-PS.WEN" "DDR4-PS.CASN" "DDR4-PS.RASN"
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	)
	(text_box "* Address, Command and Control Skew Constraints\nmax length: 1339 ps\naddress/command/control to CK: +-8 ps\nck_p and ck_n: 2 ps\n\n* Data Group Skew Constraints\nmax length: 1017 ps\ndata/dm to DQS: +-10 ps\ndqs_p and dqs_n: 2 ps\nCK to dqs: -149 to 1796 ps"
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	(text_box "ALERT_n.  Should be wired as a long fly-by connection with the device at one end. Connections are from the alert_n pin of the SDRAMs to the ALERT_N pin of the device. There is a pull-up resistor to VCCO_PSDDR at the end farthest electrically from the device."
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