(kicad_sch
	(version 20250114)
	(generator "eeschema")
	(generator_version "9.0")
	(paper "A3")
	(title_block
		(title "FPGA Main Sheet")
		(rev "-")
	)
	(lib_symbols)
	(text_box "! LVPECL not supported by this FPGA (no HR banks) !"
		(exclude_from_sim no)
		(at 85.09 95.25 0)
		(size 67.31 6.35)
		(margins 0.9525 0.9525 0.9525 0.9525)
		(fill
			(type color)
			(color 255 255 150 1)
		)
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	(junction
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		(diameter 0)
		(color 0 0 0 0)
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	(junction
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		(diameter 0)
		(color 0 0 0 0)
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	(junction
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		(diameter 0)
		(color 0 0 0 0)
	)
	(bus_entry
		(at 231.14 214.63)
		(size 2.54 2.54)
	)
	(bus_entry
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		)
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	(bus
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		)
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	(wire
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	(bus
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	(bus
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		)
	)
	(wire
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		)
	)
	(bus
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		)
	)
	(wire
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			(xy 316.23 129.54) (xy 325.12 129.54)
		)
	)
	(bus
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		)
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	(wire
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	(wire
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	(bus
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		)
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	(bus
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		)
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	(bus
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		)
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	(bus
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		)
	)
	(bus
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		)
	)
	(wire
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		)
	)
	(bus
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		)
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	(bus
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		)
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	(bus
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	(bus
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		)
	)
	(bus
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		)
	)
	(bus
		(pts
			(xy 316.23 111.76) (xy 334.01 111.76)
		)
	)
	(wire
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		)
	)
	(wire
		(pts
			(xy 241.3 202.565) (xy 261.62 202.565)
		)
	)
	(bus
		(pts
			(xy 241.3 58.42) (xy 241.3 96.52)
		)
	)
	(bus
		(pts
			(xy 241.3 96.52) (xy 261.62 96.52)
		)
	)
	(bus
		(pts
			(xy 309.88 187.96) (xy 326.39 187.96)
		)
	)
	(bus
		(pts
			(xy 237.49 58.42) (xy 241.3 58.42)
		)
	)
	(wire
		(pts
			(xy 240.03 99.06) (xy 261.62 99.06)
		)
	)
	(bus
		(pts
			(xy 316.23 148.59) (xy 321.31 148.59)
		)
	)
	(wire
		(pts
			(xy 240.03 179.07) (xy 261.62 179.07)
		)
	)
	(wire
		(pts
			(xy 326.39 221.615) (xy 309.88 221.615)
		)
	)
	(wire
		(pts
			(xy 316.23 58.42) (xy 321.31 58.42)
		)
	)
	(wire
		(pts
			(xy 316.23 74.93) (xy 321.31 74.93)
		)
	)
	(bus
		(pts
			(xy 240.03 116.84) (xy 261.62 116.84)
		)
	)
	(wire
		(pts
			(xy 316.23 72.39) (xy 321.31 72.39)
		)
	)
	(wire
		(pts
			(xy 316.23 142.24) (xy 325.12 142.24)
		)
	)
	(image
		(at 120.6915 155.227)
		(scale 0.375289)
	)
	(image
		(at 131.117 67.015)
		(scale 0.465469)
	)
	(label "GTH_BCLK_B2_N"
		(at 240.03 179.07 0)
	)
	(label "{PS-QSPI}"
		(at 243.84 223.52 0)
	)
	(label "PS_POR_B"
		(at 245.11 202.565 0)
	)
	(label "GTH_BCLK_B1_N"
		(at 240.03 133.35 0)
	)
	(label "SFP1{SFP}"
		(at 312.42 185.42 0)
	)
	(label "GTH_BCLK_B1_P"
		(at 240.03 130.81 0)
	)
	(label "GTH_BCLK_B2_P"
		(at 240.03 125.73 0)
	)
	(label "WR_CLK.RSTN"
		(at 238.76 217.17 0)
	)
	(label "GTH_BCLK_B1_N"
		(at 240.03 184.15 0)
	)
	(label "{WRFLASH_I2C}"
		(at 318.77 111.76 0)
	)
	(label "{IOEXP}"
		(at 252.73 116.84 180)
	)
	(label "{VMEF}"
		(at 246.38 58.42 0)
	)
	(label "{I2C}"
		(at 243.84 226.06 0)
	)
	(label "GTH_BCLK_B1_P"
		(at 240.03 181.61 0)
	)
	(label "{WR_DAC}"
		(at 318.77 101.6 0)
	)
	(label "WR_CLK.SI5340_IRQ_N"
		(at 238.76 219.71 0)
	)
	(label "{PCIE}"
		(at 312.42 172.72 0)
	)
	(label "SFP0{SFP}"
		(at 312.42 187.96 0)
	)
	(label "GTH_BCLK_B2_P"
		(at 240.03 176.53 0)
	)
	(label "{F_P0}"
		(at 246.38 60.96 0)
	)
	(label "{WR_CLK}"
		(at 248.92 171.45 0)
	)
	(label "{DDR4-PS}"
		(at 246.38 161.29 0)
	)
	(label "GTH_BCLK_B2_N"
		(at 240.03 128.27 0)
	)
	(label "{WR_CLK}"
		(at 245.11 111.76 0)
	)
	(label "{USERIO_A}"
		(at 245.11 106.68 0)
	)
	(hierarchical_label "SFP0_SCL"
		(shape bidirectional)
		(at 321.31 64.77 0)
	)
	(hierarchical_label "PS_UART_RXD"
		(shape output)
		(at 326.39 221.615 0)
	)
	(hierarchical_label "SFP0{SFP}"
		(shape bidirectional)
		(at 326.39 187.96 0)
	)
	(hierarchical_label "{WR_CLK}"
		(shape bidirectional)
		(at 222.25 111.76 180)
	)
	(hierarchical_label "{PCIE}"
		(shape bidirectional)
		(at 326.39 172.72 0)
	)
	(hierarchical_label "PS_UART_TXD"
		(shape input)
		(at 326.39 219.075 0)
	)
	(hierarchical_label "SFP1_SCL"
		(shape bidirectional)
		(at 321.31 72.39 0)
	)
	(hierarchical_label "{DDR4-PS}"
		(shape bidirectional)
		(at 219.71 161.29 180)
	)
	(hierarchical_label "PL_UART_RXD"
		(shape output)
		(at 325.12 132.08 0)
	)
	(hierarchical_label "PL_UART_TXD"
		(shape input)
		(at 325.12 129.54 0)
	)
	(hierarchical_label "{F_P0}"
		(shape bidirectional)
		(at 237.49 60.96 180)
	)
	(hierarchical_label "PS_POR_B"
		(shape input)
		(at 241.3 202.565 180)
	)
	(hierarchical_label "{USERIO_A}"
		(shape bidirectional)
		(at 238.76 106.68 180)
	)
	(hierarchical_label "SFP_LED_DATA"
		(shape output)
		(at 321.31 58.42 0)
	)
	(hierarchical_label "FPGA-PL_CLKSYS_N"
		(shape input)
		(at 240.03 101.6 180)
	)
	(hierarchical_label "FPGA-PL_CLKSYS_P"
		(shape input)
		(at 240.03 99.06 180)
	)
	(hierarchical_label "PP_LED0_DATA"
		(shape output)
		(at 325.12 142.24 0)
	)
	(hierarchical_label "FP_LED0_DATA"
		(shape output)
		(at 325.12 137.16 0)
	)
	(hierarchical_label "FPGA-PS_CLKREF"
		(shape input)
		(at 241.3 200.025 180)
	)
	(hierarchical_label "{I2C}"
		(shape bidirectional)
		(at 241.3 226.06 180)
	)
	(hierarchical_label "{WR_DAC}"
		(shape bidirectional)
		(at 334.01 101.6 0)
	)
	(hierarchical_label "PP_LED1_DATA"
		(shape output)
		(at 325.12 144.78 0)
	)
	(hierarchical_label "SFP1_SDA"
		(shape bidirectional)
		(at 321.31 74.93 0)
	)
	(hierarchical_label "{VMEF}"
		(shape bidirectional)
		(at 237.49 58.42 180)
	)
	(hierarchical_label "F_IO[0..31]"
		(shape bidirectional)
		(at 334.01 120.65 0)
	)
	(hierarchical_label "SFP0_SDA"
		(shape bidirectional)
		(at 321.31 67.31 0)
	)
	(hierarchical_label "{WRFLASH_I2C}"
		(shape bidirectional)
		(at 334.01 111.76 0)
	)
	(hierarchical_label "FP_LED1_DATA"
		(shape output)
		(at 325.12 139.7 0)
	)
	(hierarchical_label "{PS-QSPI}"
		(shape bidirectional)
		(at 241.3 223.52 180)
	)
	(hierarchical_label "{IOEXP}"
		(shape bidirectional)
		(at 240.03 116.84 180)
	)
	(hierarchical_label "SFP1{SFP}"
		(shape bidirectional)
		(at 326.39 185.42 0)
	)
	(sheet
		(at 261.62 93.98)
		(size 54.61 57.15)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-hp-banks"
			(at 261.62 93.2684 0)
		)
		(property "Sheetfile" "fpga-hp-banks.kicad_sch"
			(at 261.62 151.7146 0)
		)
		(pin "FPGA-PL_CLKSYS_N" input
			(at 261.62 101.6 180)
		)
		(pin "FPGA-PL_CLKSYS_P" input
			(at 261.62 99.06 180)
		)
		(pin "{WRFLASH_I2C}" bidirectional
			(at 316.23 111.76 0)
		)
		(pin "{VMEF}" bidirectional
			(at 261.62 96.52 180)
		)
		(pin "{WR_DAC}" bidirectional
			(at 316.23 101.6 0)
		)
		(pin "WR_UART_RXD" output
			(at 316.23 132.08 0)
		)
		(pin "WR_UART_TXD" input
			(at 316.23 129.54 0)
		)
		(pin "{IOEXP}" bidirectional
			(at 261.62 116.84 180)
		)
		(pin "F_IO[0..31]" bidirectional
			(at 316.23 120.65 0)
		)
		(pin "FP_LED0_DATA" output
			(at 316.23 137.16 0)
		)
		(pin "FP_LED1_DATA" output
			(at 316.23 139.7 0)
		)
		(pin "{USERIO_A}" bidirectional
			(at 261.62 106.68 180)
		)
		(pin "{WR_CLK}" bidirectional
			(at 261.62 111.76 180)
		)
		(pin "{PCIE}" bidirectional
			(at 316.23 148.59 0)
		)
		(pin "PP_LED0_DATA" output
			(at 316.23 142.24 0)
		)
		(pin "PP_LED1_DATA" output
			(at 316.23 144.78 0)
		)
		(pin "GTH_BCLK_B1_P" input
			(at 261.62 130.81 180)
		)
		(pin "GTH_BCLK_B2_P" input
			(at 261.62 125.73 180)
		)
		(pin "GTH_BCLK_B2_N" input
			(at 261.62 128.27 180)
		)
		(pin "GTH_BCLK_B1_N" input
			(at 261.62 133.35 180)
		)
		(instances
			(project "vme-wren"
				(path
					(page "3")
				)
			)
		)
	)
	(sheet
		(at 261.62 234.315)
		(size 48.26 6.35)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-power"
			(at 261.62 231.775 0)
		)
		(property "Sheetfile" "fpga-power.kicad_sch"
			(at 261.62 234.315 0)
		)
		(instances
			(project "vme-wren"
				(path
					(page "10")
				)
			)
		)
	)
	(sheet
		(at 260.35 55.88)
		(size 55.88 29.21)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-hd-banks"
			(at 260.35 55.1684 0)
		)
		(property "Sheetfile" "fpga-hd-banks.kicad_sch"
			(at 260.35 85.6746 0)
		)
		(pin "{VMEF}" bidirectional
			(at 260.35 58.42 180)
		)
		(pin "{F_P0}" bidirectional
			(at 260.35 60.96 180)
		)
		(pin "SFP_LED_DATA" output
			(at 316.23 58.42 0)
		)
		(pin "SFP1_SDA" bidirectional
			(at 316.23 74.93 0)
		)
		(pin "SFP0_SDA" bidirectional
			(at 316.23 67.31 0)
		)
		(pin "SFP1_SCL" bidirectional
			(at 316.23 72.39 0)
		)
		(pin "SFP0_SCL" bidirectional
			(at 316.23 64.77 0)
		)
		(instances
			(project "vme-wren"
				(path
					(page "4")
				)
			)
		)
	)
	(sheet
		(at 261.62 215.265)
		(size 48.26 12.7)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-mio"
			(at 261.62 212.725 0)
		)
		(property "Sheetfile" "fpga-mio.kicad_sch"
			(at 261.62 215.265 0)
		)
		(pin "{PS-QSPI}" bidirectional
			(at 261.62 223.52 180)
		)
		(pin "PS_UART_RXD" output
			(at 309.88 221.615 0)
		)
		(pin "PS_UART_TXD" input
			(at 309.88 219.075 0)
		)
		(pin "WR_CLK_RSTN" output
			(at 261.62 217.17 180)
		)
		(pin "WR_CLK_SI5340_IRQ_N" input
			(at 261.62 219.71 180)
		)
		(pin "{I2C}" bidirectional
			(at 261.62 226.06 180)
		)
		(instances
			(project "vme-wren"
				(path
					(page "5")
				)
			)
		)
	)
	(sheet
		(at 261.62 158.75)
		(size 48.26 5.08)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-ps-ddr"
			(at 261.62 156.21 0)
		)
		(property "Sheetfile" "fpga-ps-ddr.kicad_sch"
			(at 261.62 158.75 0)
		)
		(pin "{DDR4-PS}" bidirectional
			(at 261.62 161.29 180)
		)
		(instances
			(project "vme-wren"
				(path
					(page "8")
				)
			)
		)
	)
	(sheet
		(at 261.62 197.485)
		(size 48.26 12.7)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-config"
			(at 261.62 194.945 0)
		)
		(property "Sheetfile" "fpga-config.kicad_sch"
			(at 261.62 197.485 0)
		)
		(pin "FPGA-PS_CLKREF" input
			(at 261.62 200.025 180)
		)
		(pin "PS_POR_B" input
			(at 261.62 202.565 180)
		)
		(instances
			(project "vme-wren"
				(path
					(page "9")
				)
			)
		)
	)
	(sheet
		(at 261.62 168.91)
		(size 48.26 21.59)
		(exclude_from_sim no)
		(in_bom yes)
		(on_board yes)
		(dnp no)
		(fields_autoplaced yes)
		(fill
			(color 255 255 255 1.0000)
		)
		(property "Sheetname" "fpga-mgts"
			(at 261.62 168.1984 0)
		)
		(property "Sheetfile" "fpga-mgts.kicad_sch"
			(at 261.62 191.0846 0)
		)
		(pin "{WR_CLK}" bidirectional
			(at 261.62 171.45 180)
		)
		(pin "SFP1{SFP}" bidirectional
			(at 309.88 185.42 0)
		)
		(pin "SFP0{SFP}" bidirectional
			(at 309.88 187.96 0)
		)
		(pin "{PCIE}" bidirectional
			(at 309.88 172.72 0)
		)
		(pin "GTH_BCLK_B2_P" output
			(at 261.62 176.53 180)
		)
		(pin "GTH_BCLK_B2_N" output
			(at 261.62 179.07 180)
		)
		(pin "GTH_BCLK_B1_P" output
			(at 261.62 181.61 180)
		)
		(pin "GTH_BCLK_B1_N" output
			(at 261.62 184.15 180)
		)
		(instances
			(project "vme-wren"
				(path
					(page "6")
				)
			)
		)
	)
)
