{
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          "height": 1.5,
          "width": 1.5
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      },
      "diff_pair_dimensions": [],
      "drc_exclusions": [],
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      },
      "rule_severities": {
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        "clearance": "error",
        "connection_width": "warning",
        "copper_edge_clearance": "error",
        "copper_sliver": "warning",
        "courtyards_overlap": "error",
        "creepage": "error",
        "diff_pair_gap_out_of_range": "error",
        "diff_pair_uncoupled_length_too_long": "error",
        "drill_out_of_range": "error",
        "duplicate_footprints": "warning",
        "extra_footprint": "warning",
        "footprint": "error",
        "footprint_filters_mismatch": "ignore",
        "footprint_symbol_mismatch": "warning",
        "footprint_type_mismatch": "ignore",
        "hole_clearance": "error",
        "hole_near_hole": "error",
        "hole_to_hole": "error",
        "holes_co_located": "warning",
        "invalid_outline": "error",
        "isolated_copper": "warning",
        "item_on_disabled_layer": "error",
        "items_not_allowed": "error",
        "length_out_of_range": "error",
        "lib_footprint_issues": "ignore",
        "lib_footprint_mismatch": "warning",
        "malformed_courtyard": "error",
        "microvia_drill_out_of_range": "error",
        "mirrored_text_on_front_layer": "warning",
        "missing_courtyard": "ignore",
        "missing_footprint": "warning",
        "net_conflict": "warning",
        "nonmirrored_text_on_back_layer": "warning",
        "npth_inside_courtyard": "ignore",
        "padstack": "error",
        "pth_inside_courtyard": "ignore",
        "shorting_items": "error",
        "silk_edge_clearance": "warning",
        "silk_over_copper": "ignore",
        "silk_overlap": "warning",
        "skew_out_of_range": "error",
        "solder_mask_bridge": "error",
        "starved_thermal": "error",
        "text_height": "warning",
        "text_thickness": "warning",
        "through_hole_pad_without_hole": "error",
        "too_many_vias": "error",
        "track_angle": "error",
        "track_dangling": "warning",
        "track_segment_length": "error",
        "track_width": "error",
        "tracks_crossing": "error",
        "unconnected_items": "error",
        "unresolved_variable": "error",
        "via_dangling": "warning",
        "zone_has_empty_net": "error",
        "zones_intersect": "error"
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      "rule_severitieslegacy_courtyards_overlap": true,
      "rule_severitieslegacy_no_courtyard_defined": false,
      "rules": {
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        "allow_microvias": false,
        "max_error": 0.005,
        "min_clearance": 0.0,
        "min_connection": 0.0,
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        "min_groove_width": 0.0,
        "min_hole_clearance": 0.0,
        "min_hole_to_hole": 0.25,
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        "min_microvia_drill": 0.1,
        "min_resolved_spokes": 2,
        "min_silk_clearance": 0.0,
        "min_text_height": 0.8,
        "min_text_thickness": 0.08,
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        "min_via_diameter": 0.4,
        "solder_mask_to_copper_clearance": 0.0,
        "use_height_for_length_calcs": true
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      "teardrop_options": [
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      "tuning_pattern_settings": {
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      ],
      "zones_allow_external_fillets": false,
      "zones_use_no_outline": true
    },
    "ipc2581": {
      "dist": "",
      "distpn": "",
      "internal_id": "",
      "mfg": "",
      "mpn": ""
    },
    "layer_pairs": [],
    "layer_presets": [],
    "viewports": []
  },
  "boards": [],
  "cvpcb": {
    "equivalence_files": []
  },
  "libraries": {
    "pinned_footprint_libs": [],
    "pinned_symbol_libs": []
  },
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  "net_settings": {
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      {
        "bus_width": 12,
        "clearance": 0.2,
        "diff_pair_gap": 0.25,
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        "diff_pair_width": 0.2,
        "line_style": 0,
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "Default",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "priority": 2147483647,
        "schematic_color": "rgba(0, 0, 0, 0.000)",
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        "via_diameter": 0.6,
        "via_drill": 0.4,
        "wire_width": 6
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    ],
    "meta": {
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    },
    "net_colors": null,
    "netclass_assignments": null,
    "netclass_patterns": []
  },
  "pcbnew": {
    "last_paths": {
      "gencad": "",
      "idf": "",
      "netlist": "Test.net",
      "plot": "",
      "pos_files": "",
      "specctra_dsn": "",
      "step": "",
      "svg": "",
      "vrml": ""
    },
    "page_layout_descr_file": ""
  },
  "schematic": {
    "legacy_lib_dir": "",
    "legacy_lib_list": []
  },
  "sheets": [],
  "text_variables": {}
}
