(kicad_pcb (version 20200512) (host pcbnew "(5.99.0-1700-gd72a778f1)")
  (general
    (thickness 1.6)
    (drawings 4)
    (tracks 14)
    (modules 2)
    (nets 4)
  )
  (paper "A4")
  (layers
    (0 "F.Cu" signal)
    (31 "B.Cu" signal)
    (32 "B.Adhes" user)
    (33 "F.Adhes" user)
    (34 "B.Paste" user)
    (35 "F.Paste" user)
    (36 "B.SilkS" user)
    (37 "F.SilkS" user)
    (38 "B.Mask" user)
    (39 "F.Mask" user)
    (40 "Dwgs.User" user)
    (41 "Cmts.User" user)
    (42 "Eco1.User" user)
    (43 "Eco2.User" user)
    (44 "Edge.Cuts" user)
    (45 "Margin" user)
    (46 "B.CrtYd" user)
    (47 "F.CrtYd" user)
    (48 "B.Fab" user)
    (49 "F.Fab" user)
  )
  (setup
    (stackup
      (layer "F.SilkS" (type "Top Silk Screen"))
      (layer "F.Paste" (type "Top Solder Paste"))
      (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
      (layer "F.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
      (layer "B.Cu" (type "copper") (thickness 0.035))
      (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
      (layer "B.Paste" (type "Bottom Solder Paste"))
      (layer "B.SilkS" (type "Bottom Silk Screen"))
      (copper_finish "None")
      (dielectric_constraints no)
    )
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (clearance_min 0.15)
    (via_min_annulus 0.05)
    (via_min_size 0.4)
    (through_hole_min 0.3)
    (via_size 0.8)
    (via_drill 0.4)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (max_error 0.005)
    (defaults
      (edge_clearance 0.01)
      (edge_cuts_line_width 0.05)
      (courtyard_line_width 0.05)
      (copper_line_width 0.2)
      (copper_text_dims (size 1.5 1.5) (thickness 0.3))
      (silk_line_width 0.12)
      (silk_text_dims (size 1 1) (thickness 0.15))
      (fab_layers_line_width 0.1)
      (fab_layers_text_dims (size 1 1) (thickness 0.15))
      (other_layers_line_width 0.1)
      (other_layers_text_dims (size 1 1) (thickness 0.15))
      (dimension_units 0)
      (dimension_precision 1)
    )
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.05)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes true)
      (usegerberadvancedattributes true)
      (creategerberjobfile true)
      (svguseinch false)
      (svgprecision 6)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (sketchpadsonfab false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory "")
    )
  )
  (net 0 "")
  (net 1 "Net-(J1-Pad1)")
  (net 2 "Net-(J1-Pad2)")
  (net 3 "Net-(J1-Pad3)")
  (net_class "Default" "This is the default net class."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.8)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(J1-Pad1)")
    (add_net "Net-(J1-Pad2)")
    (add_net "Net-(J1-Pad3)")
  )
  (module "Resistors_SMD:R_0805" (layer "B.Cu") (tedit 58E0A804)
    (at 120.6246 66.2432 -90)
    (descr "Resistor SMD 0805, reflow soldering, Vishay (see dcrcw.pdf)")
    (tags "resistor 0805")
    (attr smd)
    (fp_text reference "R1" (at 0 1.65 -90) (layer "B.SilkS"))
    (fp_text value "R" (at 0 -1.75 -90) (layer "B.Fab"))
    (fp_text user "${REFERENCE}" (at 0 0 -90) (layer "B.Fab"))
    (pad "1" smd rect (at -0.95 0 270) (size 0.7 1.3) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 2 "Net-(J1-Pad2)"))
    (pad "2" smd rect (at 0.95 0 270) (size 0.7 1.3) (layers "B.Cu" "B.Paste" "B.Mask")
      (net 1 "Net-(J1-Pad1)"))
    (model "${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0805.wrl"
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module "Connectors_JST:JST_SH_SM03B-SRSS-TB_03x1.00mm_Angled" (layer "F.Cu") (tedit 56B07436)
    (at 129.4384 68.7324 45)
    (descr "http://www.jst-mfg.com/product/pdf/eng/eSH.pdf")
    (tags "connector jst sh")
    (attr smd)
    (fp_text reference "J1" (at -1 -4 45) (layer "F.SilkS"))
    (fp_text value "Conn_01x03_MountingPin" (at 0 4.5 45) (layer "F.Fab"))
    (pad "1" smd rect (at -1 -1.9375 45) (size 0.6 1.55) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "Net-(J1-Pad1)") (pinfunction "Pin_1"))
    (pad "2" smd rect (at 0 -1.9375 45) (size 0.6 1.55) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 2 "Net-(J1-Pad2)") (pinfunction "Pin_2"))
    (pad "3" smd rect (at 1 -1.9375 45) (size 0.6 1.55) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 3 "Net-(J1-Pad3)") (pinfunction "Pin_3"))
    (pad "" smd rect (at -2.3 1.9375 45) (size 1.2 1.8) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad "" smd rect (at 2.3 1.9375 45) (size 1.2 1.8) (layers "F.Cu" "F.Paste" "F.Mask"))
  )
  (gr_line (start 117.3988 76.708) (end 117.221 61.4934) (layer "Edge.Cuts") (width 0.05))
  (gr_line (start 144.526 76.7334) (end 117.3988 76.708) (layer "Edge.Cuts") (width 0.05))
  (gr_line (start 144.4752 61.4934) (end 144.526 76.7334) (layer "Edge.Cuts") (width 0.05))
  (gr_line (start 117.221 61.4934) (end 144.4752 61.4934) (layer "Edge.Cuts") (width 0.05))
)
